A structure of a conventional vertical type MOS field effect transistor (i.e., a vertical type MOSFET) or the like is shown in FIG. 11 (See Japanese Patent Application Publication No. 2002-184985). In the structure, a N conductive type semiconductor region 2 and a P conductive type semiconductor region 3 are disposed in a trench having a predetermined depth in a substrate depth direction. These regions 2, 3 are alternately aligned on a semiconductor substrate 1. This is a columnar structure known as “a super-junction structure.” A column region 4 having the columnar structure is formed on the semiconductor substrate 1. An active region 13 is formed on the column region 4 so that a device structure having high breakdown voltage and low on-state resistance is provided. The active region 13 is composed of a source region 7, a gate region 11 and a body region 6.
In an outer periphery 141 of the column region, it is important to increase a breakdown voltage at a connection between a N conductive type semiconductor region (i.e., a N conductive type column region 2) and a P conductive type semiconductor region (i.e., a P conductive type column region 3). Accordingly, the conventional vertical type MOSFET has a cross section, in which the N conductive type column region 2 and the P conductive type column region 3 are aligned on the semiconductor substrate 1 alternately. A distance from an utmost outer periphery of the active region 13 to a terminal end 16 of the column region 4 is equal to or larger than a depth of the column region 4.
FIG. 2A is a layout chart showing the column region 4, which is constructed such that the N conductive type column region 2 and the P conductive type column region 3 are alternately aligned on the semiconductor substrate.
A shown in FIG. 2A, the P conductive type column region 3 is constructed such that multiple regions are aligned as a rectangular striped shape, and each region has a polygonal shape. Here, the polygon having the rectangular striped shape has a pair of wide sides, which face each other. Further, the polygon has another pair of narrow sides, which are disposed on both ends of the wide sides. Accordingly, for example, in case of a quadrangle, the polygon is obtained by spreading one pair of facing sides of the quadrangle having two pair of facing sides. The spread sides provide wide sides, and the other sides provide narrow sides. In a case where the polygon is a hexagon, one pair of facing sides is spread so that the one pair of spread sides provides a pair of wide sides, and the other two pairs of facing sides provide two pairs of narrow sides. Here, in FIG. 2A, the active region 13 is shown as a dashed line so that the positioning relationship of the active region 13 is clearly defined.
Conventionally, a structure having a cross section along with line IA—IA in FIG. 2A is well-known. The IA—IA cross section corresponds to a region facing the wide side of the P conductive type column region in the structure, in which the N conductive type column region 2 and the P conductive type column region 3 are alternately aligned with a rectangular striped shape on the semiconductor substrate.
However, it has not studied substantially about an effective structure of a structure corresponding to the IB—IB cross section shown in FIG. 2B. The IB—IB cross section corresponds to the region facing the narrow side of the P conductive type column region 3. On the substrate surface, it is obvious that the breakdown voltage becomes larger as the distance from the utmost outer periphery of the active region 13 to the terminal end of the column region 4 becomes longer. In general, it is required for the semiconductor device to become minimized. Therefore, it is required to produce a condition for meeting with a small sized device having high breakdown voltage and low on-state resistance.
In view of the above problem, it is an object of the present invention to provide a structure providing a small sized device having sufficient breakdown voltage and sufficient on-state resistance in a high breakdown voltage semiconductor device, in which a N conductive type column region and a P conductive type column region are alternately aligned on a semiconductor substrate.